Totally Self-Checking FPGA-based FSM

Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA Implemetation

Highly Reliable Design Based on Tsc Circuits

This paper deals with architecture of highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. A duplex system is used as a basic structure of this reliable design. The whole design implemented in FPGA is divided into individual functional parts. Every part is modified to ensure totally self checking properties, which are calculated using our method of detail...

Synthesis of ASM-based Self-Checking Controllers

In this paper we present a new technique for on-line checking of FPGA-based sequential devices defined by their algorithmic state machines (ASMs). The technique utilizes specific properties of ASMs for achieving the totally self-checking goal with a low hardware overhead. This technique is based on the architecture that consists of two portions: a self-checking sequential device and a separate ...

Implementation and Delay Estimation of Concurrent Error Detection Arithmetic Adders Using Hardware Redundancy Based on Dual Rail Encoding

Arithmetic functions are the most used operations in VLSI circuits. So the design of adders with high reliability and speed operation are of major concern in such circuits. This paper presents a methodology for designing totally self-checking Arithmetic adders for VLSI circuits and FPGA implementation using Verilog HDL. It detects the presence of all single stuck-at faults on-line that may occu...

Design Automation of Fpga Based Reliable Checkers

This work presents a CAD tool incorporating several approaches to the design of reliable checkers for totally self checking control units. Some of the approaches are original. To achieve the required properties, unidirectional error detecting codes are applied to the outputs of the control units. Traditionally, minimum check bits in the code serves as the criterion for its selection. The new pr...